1. Difference between inter assignment and intra assignment delay
2. Blocking and Non- blocking procedural block
3. How to design AND gate using MUX
4. Signals used in FIFO.
5. Do FIFO required address or not?
6. What do you understand by synchronous and asynchronous circuit.
7. How can we disable the randomisation ?
8. Why we use virtual interface in verification environment?
9. How to select and give in the particular testcase which were generated in generator block?

Question

1. Difference between inter assignment and intra assignment delay
2. Blocking and Non- blocking procedural block
3. How to design AND gate using MUX
4. Signals used in FIFO.
5. Do FIFO required address or not?
6. What do you understand by synchronous and asynchronous circuit.
7. How can we disable the randomisation ? 
8. Why we use virtual interface in verification environment?
9. How to select and give in the particular testcase which were generated in generator block?

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