1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners.

2. An interesting question about how latency affects jitter.

3. Maximums kew allowed when lock up latches are used.

4. OCV n questions based on it.

5. CRPR.

6. how does a cell get min n max delay?

7. spef file contents, questions about star-rd extractor working.

8. Internship exp based questions.

Question

1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners.

2. An interesting question about how latency affects jitter.

3. Maximums kew allowed when lock up latches are used.

4. OCV n questions based on it.

5. CRPR.

6. how does a cell get min n max delay?

7. spef file contents, questions about star-rd extractor working.

8. Internship exp based questions.

Anonymous · Accepted Answer

All the questions required some good thinking.

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