Illumina Interview Question
In an FPGA how would you move data bus from one clock domain to another
Interview Answer
Anonymous
Sep 29, 2013
Use an asynchronous FIFO and use empty and full flags to prevent overflow and underflow
In an FPGA how would you move data bus from one clock domain to another
Anonymous
Use an asynchronous FIFO and use empty and full flags to prevent overflow and underflow
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