Cirrus Logic Interview Question: Verilog question with additional requirements. Design a FSM providing fibonacci sequence with enable and reset. Output should be immediate.

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Cirrus Logic Digital Design Engineer interview

Cirrus Logic Interview Question

Digital Design Engineer Interview

Verilog question with additional requirements. Design a FSM providing fibonacci sequence with enable and reset. Output should be immediate.

Interview Answers

Anonymous

Nov 5, 2011

Two registers storing last two numbers in sequence with adding circuit muxed with the enable signal. Combinational output from mux. Answer should be in verilog code.

Anonymous

Jun 2, 2016

This is actually another way of asking: what is the difference of blocking and non blocking assignment. and the key point in this question is to use the non blocking assignment

Cirrus Logic interviews

Cirrus Logic

Cirrus Logic Interview Question

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