Microsoft's Quantum team is building the first scalable, fault-tolerant quantum computer, advancing everything from quantum hardware and error correction to Azure integration. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. As quantum computing enters a pivotal phase of accelerated growth, this position offers a unique opportunity to contribute meaningfully to a transformative technology, such as the Application Specific Integrated Circuits (ASICs) and analog circuitry developed by this team.

As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog Layout designs and coordinating employees, contingent staff, and external vendors to deliver high-quality designs.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

• Deliver Schematic-to-Graphic Database System (GDS) layouts for cutting-edge, high-performance, high-speed, low-power IP designs, including interconnectivity solutions and foundational Analog circuit blocks. Execute these layouts across multiple process nodes, including deep Fin Field-Effect Transistor (FinFET), following industry best practices.
• Develop plans for Analog Mask Layout execution and follow processes and methodologies to deliver IP blocks. Coordinate tasks with junior layout team members as needed.
• Using Cadence Virtuoso (or other equivalent) design tools and flows; perform layout implementation of analog-intensive IPs and help establish flows, methodologies, and processes for execution alongside peers.
• Support the on-boarding and off-boarding of contingent layout staff and vendor partners as needed; help direct their day-to-day execution to ensure quality and schedule are met.
• Work with other members of the team to deliver IPs, including project planning, schedule tracking, and report generation. Follow, augment, or put in place processes and methodologies for high-quality execution alongside peers.
• Other
  • Embody our culture and values.

Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.