The Opportunity: 4 month work term (Aug/Sept - Dec, 2026)

How You Will Contribute:

As a successful candidate, you will be working within the ASIC IP team with other design and verification engineers, performing digital ASIC design and verification of the Client sub-systems and cores.

The Client team crafts, develops, and tests the client protocol mapping IP of Ciena’s industry leading Wavelogic coherent engine Chipsets. Wavelogic ASICs are widely used in Ciena products, and they are one of the main contributors to Ciena’s success.

During your coop term in our team, you will learn about many aspects of the digital ASIC development such as our design and verification environment, prototype development, and development automation. You will be assigned well defined tasks that will allow you to contribute to our team and broaden your knowledge and gain experience in optical networking and digital ASIC development.

RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA-based validation. You will gain in-depth knowledge of many communications standards from IEEE 802.3, ITU, and OIF, as well as understanding system wide concepts.

Work as a team member that is responsible for the design and verification of complex digital blocks and subsystems

Implement and verify digital designs using System Verilog/UVM

The Must Haves:

• Good academic standing in a Bachelor’s degree program in Electrical Engineering or Computer Engineering

• Previous experience with ASIC or FPGA development, as well as knowledge of and experience using System Verilog, Verilog, VHDL and Python

• Strong verbal and technical writing skills

• Self-motivated, and the ability to work independently as well as in a team environment

Assets:

• Knowledge of OTN, Ethernet, and other Optical Networking standards

• Strong problem solving and debugging skills

• Experience working in a Linux environment

Pay Range:

The hourly pay range for this position is $27.00 - $37.50