Job Title: Physical Design Engineer (PD/PnR)
City: Sunnyvale, Mountain View
State/Province: California
Posting Start Date: 7/21/26
Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Role Purpose

Job Summary
Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoC designs.
Key Responsibilities

• Perform block-level and top-level Physical Design implementation using Fusion Compiler.
• Drive floorplanning, placement, CTS, routing, and timing closure.
• Execute and analyze Static Timing Analysis (STA) across multiple corners and modes.
• Implement and verify low-power designs using UPF, including isolation, level shifters, retention, and power domain checks.
• Support physical signoff activities such as DRC, LVS, IR drop, and EM analysis.
• Collaborate with RTL, DFT, Power, and Signoff teams to achieve PPA targets.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Strong experience in Physical Design and PnR flows.
• Hands-on expertise with Synopsys Fusion Compiler.
• Solid understanding of STA, timing closure, and MMMC methodologies.
• Experience with low-power implementation and verification flows.
• Good scripting skills in Tcl, Perl, or Python.

Preferred

• Experience with advanced technology nodes (7nm and below).
• Exposure to full-chip integration and signoff methodologies.
• Strong debugging and problem-solving skills.

Mandatory Skills: VLSI Physical Place and Route .

Experience: 3-5 Years .

The expected compensation for this role ranges from $45,000 to $121,000 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.

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