Sr. Failure Analysis Engineer

• Lead and conduct complex failure analysis (FA) on DRAM modules and memory subsystems, utilizing high-speed signal integrity tools and oscilloscopes.
• Drive the determination of failure root causes at the chip, module, and system level, presenting findings to technical and leadership teams.
• Architect and execute debug strategies for system-level failures by analyzing memory controller interactions, BIOS tuning, and DIMM register settings in server and cloud environments.
• Investigate and resolve critical performance bottlenecks, intermittent failures, and memory errors caused by power integrity (PI), signal integrity (SI), and thermal stress.
• Lead the development and implementation of advanced stress test strategies for high-performance DRAM modules.
• Mentor junior engineers in best practices for high-frequency waveform analysis, signal integrity debugging, and root cause analysis.
• Generate and present detailed reports (8D) summarizing failure analysis findings, root causes, and strategic recommendations for product and process improvements.
• Act as a technical lead in cross-functional teams to enhance product design, quality, and manufacturability.

• Bachelor’s degree in Electrical Engineering or a related field; Master's degree is a plus.
• 5+ years of experience in DRAM module burn-in, stress testing, and failure analysis.
• Expert-level understanding of high-speed memory interfaces (DDR4, DDR5, HBM) and advanced SI/PI concepts.
• Proven track record of complex problem-solving and root cause failure analysis in a high-performance computing environment.
• Demonstrated mastery of server memory modules and system-level debugging in Linux and Windows environments.
• Expertise with high-frequency test equipment such as oscilloscopes.
• AI & Automation Fluency: Strong proficiency in applying modern generative AI tools and Agentic frameworks to real-world business problems.
• Advanced proficiency in data analysis and scripting (e.g., Python, Perl, or similar).
• Deep knowledge of JEDEC reliability standards, ECC error handling, and memory RAS (Reliability, Availability, and Serviceability) features.
• Extensive experience with BIOS tuning, memory controller optimizations, and DRAM memory training algorithms.
• Excellent communication skills with the ability to explain complex technical concepts effectively to both technical and non-technical audiences.
• Strong interpersonal and leadership skills for mentoring and driving cross-functional team interaction.