About us: What you'll do: The day-to-day:

• Own the architecture, design, and implementation of FPGA based digital systems
• Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions
• Integrate and deploy designs on FPGA and FPGA SoC platforms
• Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
• Develop timing constraints, analyze timing results, and implement design changes required to close timing
• Support bring up, integration, and debug in the lab using logic analyzers, scopes, and other instrumentation
• Participate and lead system level trade studies, FPGA utilization, design, and code reviews
• Maintain and control FPGA code revision history
• Create clear documentation and support test, validation, and production efforts
• Contribute to improving FPGA design standards, workflows, and development practices
• Works autonomously with little instruction to solve well-defined problems

What you'll need:

• Bachelor Degree in Electrical Engineering, Computer Engineering or a related field
• 6+ years FPGA design experience, including Xilinx Vivado
• Strong knowledge of System Verilog and/or VHDL
• Foundational knowledge of digital logic and timing considerations
• Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
• Experience with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify
• Proven track record to design and implement FPGA modules with simulation and testbench development
• Experience designing and coding for re-use, maintainability and scalability
• Experienced in the use of lab equipment including logic analyzers, DMM, spectrum analyzers
• Ability to read schematics and work closely with hardware design teams
• Good oral and written communications skills
• US citizenship
• Ability to travel up to 10%

What will help you on the job:

• MSEE degree preferred
• Familiarity with TCL, Perl, Python or another scripting language
• Experience with high-speed interfaces like SERDES, DDR2/3/4, LVDS
• System Verilog design verification techniques, UVM, or other sophisticated verification methodologies
• RTL optimization
• Experience and familiarity with Linux-based development environments
• Experience with GitHub
• Experience with Matlab
• Familiarity with CI/CD practices
• Familiarity with AI Agents (e.g. Copilot, Claude, Cursor, etc.)
• Strong troubleshooting skills
• Understanding and knowledge of Satellite communication waveforms and standards

Salary range: $132,500.00 - $209,500.00 / annually. For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $164,500.00- $246,500.00/ annually : At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat’s comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits. EEO statement: