What you'll be doing:

• Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.

• Architect voltage noise mitigation across the full stack - silicon, package, board, platform - and lead the codesign tradeoffs between them.

• Co-design noise features with Speed/Power/Reliability, circuit, power-arch, ASIC, and platform teams. You're the connective tissue across the codesign web.

• Build and lead the Sim-to-Si correlation methodology for voltage noise.

• Model and prototype next-gen noise features - transient sense, droop response, mitigation IP.

• Lead show-stopper noise bugs during bringup.

• Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal boundary work, where the highest-leverage innovation lives.

What we need to see:

• BS, MS, or PhD in EE, CE, or related (or equivalent experience) with 12+ years in silicon power integrity, voltage noise, or PDN

• Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, or decap budgeting.

• Hands-on silicon experience: bring-up, characterization, correlation — comfortable on a bench with scopes, probes, and DAQ, and in front of a simulator.

• Strong Sim-to-Si correlation instincts — the rigor of knowing which side of the equal sign is wrong, and the independence to say so.

• Proven use of AI techniques to accelerate power integrity work includes noise modeling, transient prediction, Sim-to-Si analysis, and automated correlation checks. Clear judgment is required to know where the model is conscientious and where manual measurement is vital.

• Multi-functional collaboration and spec subject area: able to drive a decision through multiple partners, detail it, and own it through sign-offs.

Ways to stand out from the crowd:

• Proof of craft: patents, publications, or reusable methodology you built in power integrity, PDN, or di/dt — artifacts that show how you think, not just what you shipped.

• Hands-on experience with groundbreaking GPU, CPU, or AI accelerator silicon at advanced nodes; multi-rail, multi-domain PDN ownership at SoC level (die + package + board co-optimization in production).

• A track record of applying ML or AI to noise modeling, transient prediction, droop response, or feature optimization — with the validation rigor to know when the model is wrong.

The best engineers on this team can describe a noise trade-off they made that nobody else in the room had yet framed. We are looking for the person who brings that clarity to NVIDIA's next generation — come tell us what you have built and how you think about these problems. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

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