Responsibilities will include, but are not limited to:

• Own and deliver critical High Bandwidth Memory (HBM) design blocks and subsystems from architectural definition through schematic, implementation, verification, tape-out, and post-silicon debug.
• Drive robust, high-performance designs by balancing performance, power, reliability, yield, and manufacturability trade-offs.
• Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues across circuit design, architecture, process integration, and packaging interactions.
• Serve as technical project lead for one or more HBM programs, coordinating execution across architecture, layout, verification, validation, process integration, packaging, test, and product engineering teams.
• Define and communicate technical strategy, priorities, and execution plans while proactively identifying risks, dependencies, and schedule impacts.
• Research, develop, and influence next-generation HBM architectures aligned with artificial intelligence, machine learning, and high-performance computing workloads.
• Apply deep knowledge of Dynamic Random-Access Memory (DRAM) operation, Joint Electron Device Engineering Council (JEDEC) specifications, memory subsystems, and high-speed interfaces to architect scalable, future-ready solutions.
• Mentor engineers through design reviews, architectural guidance, and hands-on problem-solving while driving improved design methods, best practices, and execution discipline across HBM programs.

Minimum Qualifications:

• 15+ years of experience in DRAM, HBM, advanced memory, system-on-chip, or application-specific integrated circuit design roles.
• Proven experience delivering complex designs from architecture through silicon bring-up and post-silicon debug.
• Strong expertise in DRAM operation and JEDEC standards, preferably including HBM product families.
• Extensive experience with complementary metal-oxide-semiconductor circuit design, transistor-level design, and semiconductor device physics.
• Demonstrated technical project leadership across multidisciplinary engineering teams.

Preferred Qualifications:

• Experience with digital design using Register Transfer Level methodologies such as Verilog, or similar.
• Experience with analog modeling and simulation tools such as FastSpice, HSPICE, or similar.
• Deep technical expertise in one or more areas such as DRAM memory array design, high-speed clocking and interface design, logic and custom circuit design, or power delivery optimization.
• Exposure to 2.5D or 3D packaging technologies, including through-silicon vias, hybrid bonding, or interposers.
• Strong communication skills, with the ability to explain complex technical concepts to engineers, leaders, and customers.