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76 Lead rtl design engineer jobs in United States
- Lead ASIC Digital Design Engineer
General Dynamics Mission SystemsAnnapolis Junction, MD$177K - $187K (Employer provided)Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field.…30d+ - Master Physical Design Engineering Lead (up to $800k pkg)
ASGN IncorporatedFort Collins, CO$800K (Employer provided)Hands on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packaging.…16d - Lead SoC Design Engineer - Edge AI, High-Performance ASICASGN IncorporatedLos Altos, CA$200K - $300K (Employer provided)We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process.…8d
- Principal Physical Design Engineering Lead ($400-500k)ASGN IncorporatedFort Collins, CO$230K (Employer provided)Hands on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packaging.…17d
- Lead SoC ArchitectASGN IncorporatedLos Altos, CA$200K - $300K (Employer provided)The Lead SoC Architect will lead cross-functional technical teams, work with silicon and IP partners, and guide implementation from specification through……8d
- Lead Software Engineer - Python/React, Ansible, RHEL
JPMorganChaseColumbus, OH$124K - $175K (Employer provided)Best Places to WorkStrong experience building web applications with React (component design, state management, API integration). Provide senior technical leadership and execution……28d - Sr. Principal Digital Design Verification Lead
Northrop GrummanSan Diego, CA$142K - $213K (Employer provided)Best Places to WorkBachelor’s degree in Electrical Engineering, Computer Engineering, or another STEM field and 8 years of relevant experience; or Master's degree in Electrical……8d - FPGA Design - Lead Research Engineer "CLEARANCE REQUIRED"
GE VernovaNiskayuna, NY$98K - $164K (Employer provided)Leverage FPGA design tools to develop, simulate, test, and optimize real-time embedded systems. As an FPGA Design Research Engineer, you will have the……30d+ - Camera DE Lead Engineer
QualcommSan Diego, CA$179K - $268K (Employer provided)Work closely with design verification and physical design teams to support test planning, debug, and design closure.…30d+ - DFT Technical Leader
CiscoSan Jose, CA$164K - $303K (Employer provided)Best Places to WorkNon-Metro New York state& Washington state: Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test……15d - Software Engineering Technical Leader , Frontend (Hybrid)CiscoMilpitas, CA$164K - $303K (Employer provided)Best Places to WorkNon-Metro New York state& Washington state: The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area:…30d+
- ASIC DFT STA Technical LeadCiscoSan Jose, CA$149K - $277K (Employer provided)Best Places to WorkPrior working experience with synthesis tools: Synopsys Fusion/design Compiler. You will help lead to drive the DFT and quality process through the entire……17d
- Technical Lead, Power Analysis and OptimizationCiscoSan Jose, CA$164K - $303K (Employer provided)Best Places to WorkExperience leading technical initiatives and facilitating cross-functional collaboration between design, physical design, and power analysis teams to meet PPA……30d+
- Emulation Engineer, Technical LeaderCiscoSan Jose, CA$164K - $303K (Employer provided)Best Places to WorkAssist with test plan design, test implementation, and debugging during the pre-silicon emulation process. Our team is responsible for driving integration of……30d+
- ASIC Physical Design Technical LeadCiscoSan Jose, CA$164K - $303K (Employer provided)Best Places to WorkExperience with hierarchical design, timing closure, physical design convergence, and power integrity analysis. Experience working on Fullchip activities.…30d+
- Image Sensor Digital Design Lead - PICO - SanJose
ByteDanceSan Jose, CA$213K - $450K (Employer provided)Expertise in front-end design and related EDA tools. Work with other engineers on RTL design, IP integration, verification, modeling, top-level simulation,……30d+ - Senior Principal Engineer, Chip Lead, Photonic Fabric Chiplet
Marvell TechnologySanta Clara, CA$182K - $273K (Employer provided)This role requires technical breadth across mixed‑signal SoC design, photonic integration, chiplet‑style partitioning, firmware and package‑level co‑design,……30d+ - Technical Lead, IC DesignMarvell TechnologySanta Clara, CA$182K - $273K (Employer provided)Hands-on experience for all aspects of the chip-development process, with proficiency in front-end design tools and methodologies, is a plus.…30d+
- Emulation Lead, Senior Principal EngineerMarvell TechnologySanta Clara, CA$182K - $273K (Employer provided)1324b(a)(3), all applicants may be subject to an export license review process prior to employment. To support fair and authentic hiring practices, candidates……30d+
- Mixed Signal Digital Design Lead
BroadcomFort Collins, CO$122K - $195K (Employer provided)Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.…30d+ - Lead ASIC Design EngineerBroadcomSan Jose, CA$144K - $230K (Employer provided)Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).…27d
- Senior Custom ASIC Engineering LeadBroadcomSan Jose, CA$144K - $230K (Employer provided)Hands-on experience in physical design and STA, EDA tools, design flows for physical design, logic simulation, test, and packaging.…27d
- RTL Design Sign Off LeadBroadcomFort Collins, CO$108K - $173K (Employer provided)You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the……30d+
- Lead Engineer
Quest GlobalSanta Clara, CA$130K - $140K (Employer provided)Collaborate with cross-functional teams for design closure and signoff. Experience in top-level SoC integration, signoff tools (PT, ICV), and DFM check.…14d - RTL Design and Architect leadQuest GlobalAustin, TX$104K - $145K (Glassdoor est.)Responsible for block level design, simulations, optimization, etc. Experience of working with high-speed peripheral design(DDR/PCIe/UCIe/Ethernet) team is an……29d
- Advanced ASIC Physical Design Lead
TeradyneNorth Reading, MA$192K - $308K (Employer provided)In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers,……30d+ - Chip Lead / Physical Design Director
Cadence Design SystemsAustin, TX$141K - $195K (Glassdoor est.)Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing,……30d+ - SoC Interconnect Technology Team Lead
ArmSan Diego, CA$243K - $314K (Employer provided)Exposure to network-on-chip (NoC) design methodologies and tools. Experience leading cross-functional teams and driving complex projects to tape-out.…3d - Lead FPGA EngineerAstrolabHawthorne, CA$183K - $230K (Employer provided)Perform design verification including simulations, test benches, timing analysis, and hardware testing. The ideal candidate has 10+ years of experience in FPGA……30d+
- Modelling Lead (SystemC / Virtual-Platform Architect)LumilensSan Jose, CA$124K - $201K (Glassdoor est.)Professional development opportunities and certification support. Modelling for mixed-signal or optical/SerDes systems, including control-loop / plant modelling……22d
General Dynamics Mission Systems
Lead ASIC Digital Design Engineer
Annapolis Junction, MD
$177K - $187K (Employer provided)
