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The Graphics Memory Controller (GMC) is an IP that delivers into AMD's Discrete GPU (Navi) and Instinct (HBM) based SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for an experienced, conscientious logic design engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features.

The ideal candidate for this role is an experienced and detail-oriented logic design engineer with a strong background in RTL development and a commitment to advancing graphics technologies. With over five years of experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. They are proficient in Verilog and familiar with industry-standard CAD tools from Synopsys, Cadence, and Mentor Graphics, with strong skills in simulation, synthesis, and timing analysis. This individual works effectively in dynamic, collaborative environments, communicates clearly across teams, and demonstrates strong analytical and problem-solving abilities. Their initiative and attention to detail make them a valuable contributor to AMD’s Santa Clara Design Center, where they will support the development of next-generation discrete GPUs and data center solutions.

Location: Santa Clara, CA, Rest of the US

Benefits offered are described: AMD benefits at a glance.