NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years — fueled by great technology and amazing people. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. We are seeking a skilled Senior Verification Engineer to join our Display Team and help verify the world's foremost GPU and SoC display engines! Working alongside our Architects and ASIC Engineers, you will own testplan development, verification sign-off, and infrastructure — delivering high-quality IPs that power NVIDIA products across consumer, professional, automotive, and AI markets.

• Define verification scope, develop and drive testplans (functional and performance), and build scalable UVM-based infrastructure; leverage agentic AI to automate repetitive tasks, accelerate debug, and sharpen team efficiency.

• Develop UVM testbenches and checkers; work with C/C++-based testbenches and debug reference models and designs developed in HLS; track metrics and drive coverage closure.

• Critically reason through architectural solutions and partner with our architects to develop well-crafted, silicon-proven designs.

• Collaborate across NVIDIA sites globally and work closely with external partners and customers to deploy verification flows, ensure consistent display IP behavior across diverse tool stacks, and debug complex integration issues across organizational boundaries.

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience)

• 10+ years of relevant experience.

• Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, with a passion for root-causing complex issues; experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches — ideally on shipped silicon.

• Proficiency with industry EDA tools (VCS, Verdi/Debussy, GDB) and strong software engineering practices: clean, maintainable code; version control; code review.

• Domain knowledge of display pipelines: protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low-power features (clock gating, power domains, retention, entry/exit sequences).

• Self-starter who dives into unfamiliar sub-blocks independently, communicates with clarity across time zones and organizational boundaries, and embraces agentic AI to solve daily engineering challenges and multiply team output.

• Prior Display Unit Verification experience with familiarity in pixel processing, ISO performance testing, and HLS-based designs.

• Hands-on experience verifying display protocols end-to-end, MMU/SMMU behavior under ISO traffic, and system-level low-power sequences.

• Demonstrated experience shaping architectural specifications and micro-architecture decisions — not just implementing against them.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.

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Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

Applications for this job will be accepted at least until July 27, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.