KEY RESPONSIBILITIES:

• Contribute to the definition and development of RAS features and capabilities for next‑generation GFXIP deployments.
• Assist in writing and reviewing architectural specifications related to RAS features.
• Work with senior RAS and GFXIP architects to learn and apply reliability concepts, including error detection, containment, recovery, and reporting.
• Help analyze and understand reliability metrics such as FIT, DPPM, MTBF, and MTBR, and how they trade off against performance, power, area (PPA), and security.
• Support hardware design teams in evaluating RAS protection and coverage, and in identifying gaps or improvement opportunities.
• Collaborate across SoC, RAS, and business teams to ensure RAS requirements are understood and correctly implemented.
• Experience designing, analyzing, or implementing hardware or system features in VLSI‑based designs.
• Solid understanding of digital logic, computer architecture, and hardware design fundamentals.
• Ability to read and reason about specifications, RTL, and architectural documentation.
• Good communication skills and ability to work in cross‑functional engineering teams.

• Experience in computer architecture.
• Exposure to or interest in reliability, fault tolerance, or system‑level robustness.
• Familiarity with RAS‑related concepts or mechanisms such as: Parity and ECC, Watchdog timers, Heartbeat monitors, Deferred or recoverable error handling
• Background in GPU architecture.
• Experience with RTL design a plus
• Interest in understanding failure rates and figures of merit.

• Exposure to AI/ML accelerator architectures and AI compute environments.
• Interest in reliability challenges in large-scale AI systems and accelerator deployments.

• Undergrad degree required. Bachelors, Masters or PhD degree in Computer Engineering/Electrical Engineering preferred.