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Marvell Technology ASIC Design Verification Engineer Jobs
26 results in US
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- Senior Staff Design Verification Engineer – PCIE/CXL Sub-SystemIrvine, CA$136K - $201K (Employer provided)30d+
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- Senior Staff Design Verification Engineer – Memory Sub-SystemSanta Clara, CA$134K - $201K (Employer provided)30d+
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- Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)Santa Clara, CA$35.00 - $70.00 Per Hour (Employer provided)30d+
- Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM )Santa Clara, CA$134K - $201K (Employer provided)30d+
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- Senior Principal Engineer, Chip Lead, Photonic Fabric ChipletSanta Clara, CA$182K - $273K (Employer provided)30d+