Cirrus Logic Physical Design Engineer interview questions

a lot of questions on static timing analysis with emphasis on asynchronous design. questions are like how to synchronize two blocks controlled by different clock signal. how many FFs should be added. other questions like how to deal with setup/hold time violations. some basic digital design questions such as draw a frequency divider circuit, and use an 2-1 MUX to implement a NAND gate. the interviewer was a little impatient. i got rejection email 15 minutes after the call.