Physical Design Engineer applicants have rated the interview process at Intel Corporation with 3.2 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 80% positive. To compare, the company-average is 72.9% positive. This is according to Glassdoor user ratings.
Candidates applying for Physical Design Engineer roles take an average of 26 days to get hired, when considering 41 user submitted interviews for this role. To compare, the hiring process at Intel Corporation overall takes an average of 23 days.
Common stages of the interview process at Intel Corporation as a Physical Design Engineer according to 41 Glassdoor interviews include:
Phone interview: 26%
One on one interview: 17%
Group panel interview: 11%
Skills test: 11%
Presentation: 9%
Background check: 7%
Drug test: 7%
Personality test: 6%
IQ intelligence test: 4%
Other: 1%
Here are the most commonly searched roles for interview reports -
The process took 3 days. I interviewed at Intel Corporation (Hillsboro, OR) in Apr 2011
Interview
Received an email from the Physical Design team of Intel Corporation few days back. Included details of what to be expected and what they will offer. More of layout and design on Analog/Digital/RF/IO circuits , academic background they were looking for. Didn't tell me of the duration of interview and started with HR questions followed by technical questions mostly on CMOS Digital circuits.
Interview questions [2]
Question 1
CMOS Inverter , how to reduce the drive strength of Minimum size inverter
very nice people. given 2 question one on system of the group and one for coding in binary search and recursion. we started by little talking and then a little bit on one of the project and then 2 questions
Interview questions [1]
Question 1
1. given graph and car with light sensor and we want to find the right spot of the dot on the graph. it was binary search classical
I applied online. I interviewed at Intel Corporation (Bengaluru) in May 2026
Interview
Deep whiteboard interview , was asked to draw graphs for non ideal characteristics for cmos design and pvt corners. Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
Interview questions [1]
Question 1
was asked to draw graphs for non ideal characteristics for cmos design and pvt corners.Questions related to project and physical design concepts. Focused on semiconductor physics and technical depth in each answer.
This was the second round lasted about an hour or so. The first round was mostly about my work as I had 3 year experience and I had to walk them through the projects I did etc..,.
Interview questions [1]
Question 1
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.