RFIC Design Engineer applicants have rated the interview process at Qualcomm with 3.3 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 25% positive. To compare, the company-average is 62.4% positive. This is according to Glassdoor user ratings.
Candidates applying for RFIC Design Engineer roles take an average of 24 days to get hired, when considering 6 user submitted interviews for this role. To compare, the hiring process at Qualcomm overall takes an average of 22 days.
Common stages of the interview process at Qualcomm as a RFIC Design Engineer according to 6 Glassdoor interviews include:
One on one interview: 31%
Phone interview: 23%
IQ intelligence test: 15%
Presentation: 15%
Skills test: 8%
Group panel interview: 8%
Here are the most commonly searched roles for interview reports -
I applied online. The process took 2 days. I interviewed at Qualcomm (San Diego, CA) in Nov 2012
Interview
Phone interview with one senior engineer and the hiring manager:
Senior engineer asked me the following questions:
1. How does the drain current of NMOS transistor vary with temperature change?
2. How does the gain of CS-Amplifer change with the temperature variation?
3. Basic design procedure of power amplifer?
4. Phase noise definition.
5. What cause phase noise of oscillator and PLL?
Hiring manager:
1. Cutoff frequency definition, how to calculate it of CMOS transistor, how to increase and decrease it?
2. Relationship between transconductance and width of transistor/
3. Input impedance value of CS-Amplifer with source degenerated resistor, inductor or capacitor?
4. Operational Transconductance Amplifer: How does the gain change with drain current change?
Some questions on my resume.
I applied through college or university. I interviewed at Qualcomm (Bengaluru) in Nov 2021
Interview
the first round a question on network analysis then second question about voltage swing of mos amplifier. then some question of lna and then interviwer ask about my projects and internship
Interview questions [1]
Question 1
the first round a question on network analysis then second question about voltage swing of mos amplifier. then some question of lna and then interviwer ask about my projects and internship
one phone interview, you will then be invited for on-site where you will have 1:1 with engineers. You may also need to give an hour of presentation about your past experience.
Interview questions [1]
Question 1
Basic concepts of analog design such as noise, linearity. Analog circuit questions such as calculating the gain or noise of a differential circuit.
I applied through an employee referral. The process took 3 weeks. I interviewed at Qualcomm (San Diego, CA) in Jun 2018
Interview
I had a phone screening. Few weeks later, heard from HR for onsite. I did poorly on the technical level. But honestly did very well on communicating with people and showing them my enthusiasm and excitment for their work. I received an offer.