I applied online. I interviewed at Qualcomm (San Jose, CA) in Oct 2020
Interview
The screening interviewer for this media processor group was a shady, Indian, H1B guy from Texas. He's not the hiring manager but kept asking illegally about my compensation expectation and whether I would be willing to relocate to a different location than the primary job location in Santa Clara, CA.
I answered all the technical questions properly but never heard from Qualcomm again. It baffled me about being ghosted without any updates but then I realize that this guy's intent was to block better candidates from joining his group in order to protect his position and job security at Qualcomm.
This behavior of working against his employer's interests was unfortunate and unethical but happened since one's case can be easily lost in the pool of candidates without management or HR being able to check or audit it.
Interview questions [1]
Question 1
SystemVerilog (polymorphism, constraint, assertion), UVM, test plan
I applied online. I interviewed at Qualcomm (Cork)
Interview
I applied online and was invited to a one-hour interview with a panel consisting of 2–3 engineers and the hiring manager. The interview began with an introduction to the role, followed by general questions about my background and motivation for applying. It then moved on to technical questions focused on Verilog and UVM.
I applied online. The process took 1 week. I interviewed at Qualcomm (San Diego, CA) in Nov 2024
Interview
It was two rounds, first with HR, then with the hiring manager. The first round was simple, with questions about company benefits and relocation. Second round was with more detailed questions about my past experience.
One long round of interviews. There are 6 people who interview you. Each is about 30 minutes long. They mainly ask fundamental technical questions related to transistors, current mirrors, Verilog for me. The questions are asked based on what you have on your resume.
Design Verification Engineer applicants have rated the interview process at Qualcomm with 3.1 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 63% positive. To compare, the company-average is 62.5% positive. This is according to Glassdoor user ratings.
Candidates applying for Design Verification Engineer roles take an average of 12 days to get hired, when considering 20 user submitted interviews for this role. To compare, the hiring process at Qualcomm overall takes an average of 22 days.
Common stages of the interview process at Qualcomm as a Design Verification Engineer according to 20 Glassdoor interviews include:
Phone interview: 37%
Presentation: 18%
One on one interview: 13%
Group panel interview: 11%
Skills test: 8%
Personality test: 5%
IQ intelligence test: 3%
Drug test: 3%
Background check: 3%
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