Rtl Design Engineer applicants have rated the interview process at Qualcomm with 3 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 100% positive. To compare, the company-average is 62.5% positive. This is according to Glassdoor user ratings.
Common stages of the interview process at Qualcomm as a Rtl Design Engineer according to 1 Glassdoor interviews include:
Skills test: 50%
One on one interview: 50%
Here are the most commonly searched roles for interview reports -
I applied online. I interviewed at Qualcomm in Feb 2017
Interview
It was a telephonic interview. The hiring process was online. The job posting was through linked in. After applying, a telephonic interview was scheduled. The interview mostly focused on fundamentals of digital design, RTL synthesis, implementation, PnR, STA
Interview questions [1]
Question 1
1. Given a set of specifications for register elements , how do we compute the maximum frequency of operation?
2. What are the different types of constraints used in design , when and how are they specified?
Two consecutive 1.5 hours technical interviews with tech lead/ manager.
Two 1 hour less technical more personal interviews with higher ranking managers. Technical interviews were back to back and further interviews one at a time.
Interview questions [1]
Question 1
Design a FIFO - draw block diagram. Afterwards - add simultaneous push pop, and enable instantaneous pop.
I applied online. The process took 1 week. I interviewed at Qualcomm (Bengaluru) in Nov 2022
Interview
Total 3 rounds. Each Round is 40 Minutes. First Round: Self Introduction CDC RDC Basic Questions in Verilog. Second Round: Async FIFO Logical Digital Design Questions. Third Round: About project which I worked on previous company.
Interview questions [1]
Question 1
Why Gray codes prefer instead of Binary Codes? What is Data Incoherency?