Senior RFIC Design Engineer applicants have rated the interview process at Qualcomm with 4 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 50% positive. To compare, the company-average is 62.5% positive. This is according to Glassdoor user ratings.
Candidates applying for Senior RFIC Design Engineer roles take an average of 2 days to get hired, when considering 2 user submitted interviews for this role. To compare, the hiring process at Qualcomm overall takes an average of 22 days.
Common stages of the interview process at Qualcomm as a Senior RFIC Design Engineer according to 2 Glassdoor interviews include:
One on one interview: 25%
Phone interview: 25%
Background check: 25%
Skills test: 25%
Here are the most commonly searched roles for interview reports -
I applied through an employee referral. The process took 2 days. I interviewed at Qualcomm (San Diego, CA) in May 2011
Interview
Phone interview and face to face interview, full day activity. You would meet the Qualcomm department staff one on one for about 1 hour. Questions were all different and basically covering a large part of circuit design. Both fundamental questions and quite challenging and tricky circuit questions were they were looking for very detailed and specific answers. Be prepared to do equations, qualitative analysis on the white board.
Interview questions [1]
Question 1
Many in depth technical questions about circuits, systems, testing, analog, RF
I applied through an employee referral. I interviewed at Qualcomm
Interview
Submitted my resume through referral process. Did phone interview shortly after, and was invite for on-site interview by two different groups within Qualcomm for an IC design position for as fresh Ph.D graduate. Everyone I met were very courteous and I enjoyed technical discussions with all the interviewers. I learned a great deal through the interview process as many of the engineers already have 10 to 20 years of experience on top of either M.S. or Ph.D. I was asked to present my Ph.D work first, followed by a series of interviews, each lasting about 45 minutes to an hour. Both on-site interviews lasted until 2~3 p.m. I got offers from both groups but decided to take an offer with the RF group because it seemed to fit my background better.
There were many questions that I couldn't answer with 100% certainty, so I tried to answer to the best of my ability by explaining the thought process. Overall, it was a great experience.
Interview questions [1]
Question 1
Phone interview was about 15 to 20 questions in 45 minutes. I would most definitely recommend studying Razavi's 2nd edition analog design textbook whether you are applying for RFIC or Mixed Signal. Half of questions I was asked are on fundamental things starting from MOS transistors and device physics to Op amp design and Bandgap. The other half were on my specialties. If you are a PLL designer, you will be asked synthesizer questions. If you are an ADC designer, you will be asked ADC... and so on.
Some of the questions that kept showing up through these interviews from both Qualcomm and other companies were the impedance transformation by MOSFET: what happens to the impedance of a resistor when it is in series with a MOSFET gate, drain, or source (source degeneration, input impedance of CG amplifier, CD amplifier, and so on). Bandgap will probably be asked. Impedance matching, if RFIC. I think that the outcome of the interview is highly dependent on the quality of the research presentation. If one claims to have done a design of such and such blocks, then one is expected to know pretty much everything about the block.