tell me about uvm testbench top
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.
Describe several methods for low power design
Design a two bit single cycle multiplier Write a code to check if it is palindrome or not? FSM to count the series of 1's. Single bit input per clk. Series of 1's must start and end with a 0
How do you divide clock
Design an arbiter.
What is setup/hold time?
Design some circuit using 2x1 mux only. Design a CMOS and gate
Setup and hold time for circuits
What will be the multicycle be for 0 cycle paths?
Viewing 191 - 200 interview questions