Clock Domain Crossing , RTL Design Constructs using Verilog , System Verilog and VHDL , Constraints in SDC, SDGC for spyglass
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
Explain PD flow? Questions on projects done before
Draw the contents of an asynchronous FIFO.
Async. FIFO in verilog, with relatively detailed conceptual questions
Synthesis concepts - flow, different types of libraries, process corners, some PD basics etc.
Very thorough with the technical questions. Embedded, Vlsi, ASIC, Digital Logic.
Not much. A good preparation of electronics basics, verilog and C++ languages can easily get you through the test and interview.
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