What will affect power consumption?
Asic Verification Engineer Interview Questions
274 asic verification engineer interview questions shared by candidates
questions on digital electronics and verilog
how to find if an a number is unassigned in an array?
how do you know you have cover all the case in your testbench
All kinds of fork joins
Draw the circuit base on the coding provided
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
digital, verilog, system verilog
What is your experience with random constrained stimulus?
show how code coverage and function coverage works. explain with code
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