I was given a direct coding question about how I would determine whether two patterns given to me were correct.
Design Verification Engineer Interview Questions
1,120 design verification engineer interview questions shared by candidates
1. constraints 2. assertions 3. UVM topology
Computer Architecture, Caches, Algorithms, Software Engineering
Verification plan of any given design, assertions, what is coverage?
Do you have prior experience with UVM and System Verilog
1) C++ code to set the matrix MxN to zero if any element in MxN is zero. (leetcode medium question) 2) write constraint to set 32 bit address to be word aligned and 1kb in length
Asked lots of questions about Cache and Virtual Memory, including Cache set, index, associativity, etc. CPU superscalar, Out of Order, etc. Address translation, aliasing problem
how to design a FSM using switch-case / shift register
implement blackjack with classes in python
Gave the block diagram and asked me to write interface for it
Viewing 1111 - 1120 interview questions