Implement a state machine that detects modulo 5
Design Verification Interview Questions
1,116 design verification interview questions shared by candidates
Basic stuff about Verification and assertions
Basic Computer Architecture questions. How to extend a 5 stage pipeline to 6 stages. Effects of doing that etc. A few programming questions.
DV related, protocols, sv, uvm, axi,abp
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
Lot about past experience and projects, Arbiter design, OOPS concepts, scripting, verilog, Asynchronous/synchronous FIFO, Computer Architecture, Verification concepts. However most of it was focussed on prior experience.
build a function that get: s - sum of puckets n - number of puckets MIN - minimu value of a pucket MAX - maximum value of a pucket return an array in length n that each pucket have a value between MIN and MAX and the sum of all puckets is s. all puckets are random.
32Kb cache, 2 way assoc. and 64B line. what is the cache state and line state according to MESI when. Read 0x010F30 then write 0x880F00 then write 0x010F20
They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
difference of Union and Struct (C++). VIPT cache.
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