Draw a XOR gate with CMOS.
Memory Design Interview Questions
52 memory design interview questions shared by candidates
5. Draw XOR using NAND only, with only 4 NAND gates.
1. Explain SRAM working and Noise margins of it. 2. How does PVT variation affect SRAM access times and NM. 3.Concept of Setup time and Hold time. How to fix it in Si validation. 4.Leakage current of MOSFET. How does it scale with Length, Vth and Temperature. Techniques to reduce leakage current of MOSFET (Multi Vt, DVFS, Body biasing, Header/Footer switch, Clock gating) 5. Where to use Header and Footer switch? Does FinFet has body biasing phenomenon to reduce leakage like conventional FETs. 6.Any experience with EM simulation, memory compiler design and Digital verification/STA.
Present some recent relevant circuit work.
In depth technical questions ranging from basic VLSI, logic design, CMOS, physical design & Project & presentations
SRAM bitcell ,architecture ,FOM,Sense Amp,Memory Controller,Device Physics basics,Digital Vlsi Design basics ,STA,Project based questions
How you see your self in this company? How you behave if you have lots of parallel tasks
define and discuss all types CMOS logic family
Fork join in verilog
Basics of memory design, SRAM design and margin analysis
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