Basic pd questions, logical thinking
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
Explain Semi custom flow. STA. Layout verification related.
layout related questions, and generic cmos question
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.
Explain the different regions of operation of a MOSFET
Explain the 5-stage CPU pipeline
All the concepts of STA
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
fundamental questions and design questions.
Asked setup/hold time violation and how to fix
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