Setup and hold constraints for negative and positive clock skew
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
tell me about your block
Timing analysis, digital logic design, transistor sizing and parasitics.
Transistor level details from college level courses.
Most of the question asked from Digital electronics and VLSI, CMOS.
Throughout the asic design flow., Emphasizing more on debugging and validation of results
your previous experience , Timing & clock tree basics . questions regrading floorplan
Do you prefer to work in team or independent?
Physical Designs steps!? Each steps in details.
Asic design flow, asked to explain each step briefly, drilled on the topic clock gating, power gating, glitch circuit
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