Low power implementation - UPF Level shifters, isolation cells, retention cells, clock gating, PoR sequence etc.
Rtl Design Interview Questions
212 rtl design interview questions shared by candidates
Explain and design a two level branch predictor
I could not reveal the questions
FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
Hiring managers asked about project details and tools. He was expected digital design solutions and CDC related topics. Lint and Lowpower design questions asked and given FIFO calculations. Current company job roles and responsibilities and challenges in current project
synchronization of multiple control signals FIFO Depth calculation
sync vs asyc rst
Questions were standard interview question on synthesis and lint
Most questions were from digital electronics and verilog
Design a module to return trigonometric sine value. Other question is related to the designing of the State Machine with the specified requirements.
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