Design clock switchers without any glitch.
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Calculate the number of logic 1's in a given input using combinational logic only. And some basic logic based questions
Cross clock domain synchronizer, 1 bit.
Design a hardware to detect how many bits are 1 with only combination logic design
Questions 1. Sequence detector for 1001 overlapping sequence (fsm design + verilog code) 2. Basic STA questions on setup and hold time like if in a silicon a path is failing, what would be the first step that you will do to check it is a setup failure.
Are you willing to learn new CAD software in the time you are there?
Difference Between SRAM and DRAM
What is body effect?
How many flops in FSM if you have 4 states
Which is preferred NAND or NOR? And why?
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