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Soc Design Engineer Interview Questions
114 soc design engineer interview questions shared by candidates
Pseudo code for MUX Setup and hold time
Area of the design in my past project. Best design practices. Antenna effects.
CMOS inverter questions. Power related questions
What are Setup Time and Hold time violations and how to fix them?
LRU policy, programming, state machine encoding
Draw an XOR out of NAND gates, logic minimalization, draw FSM for given signals and how many flip flops are needed to implement the design?
Basic Verilog questions, FSM, Synchronizers, Clock Domain Crossing, Sequence detectors, Clock divider circuits, FIFO, Async FIFO, Circuit to detect the number of 1's using adders and then using only combinational logic, Transpose a Matrix using C. I was asked to code on almost all of the topics mentioned above.
Some system verilog Questions
Basically covered VLSI basics, ASIC flow basics (each step) and scripting. Friendly chat for behavioral interview.
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