System Verilog Assertions.
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
they asked about UVM architecture and classes concept .
Write a decimal to hex function in C
There's a circuit diagram of two parallel capacitors with different charge voltages, connected by a transistor. What happens to those two voltages when the transistor turns on?
build a 8 to 1 multiplexer with 2 to 1 multiplexer. use minimal number of components
What is the problem of cache coherency
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
Simplify the following circuit: One adder takes A and B as input, another adder takes C and D as input. Both adder's output connects to a MUX controlled by signal S, and the output of the MUX goes into a FF
A packet with address, and data. The address range is split into 4 regions. Create a class that will generate 100 packets and cover all possible ranges.
What I know about verilog
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