Most of the things were on ARM architecture, AMBA protocols, SV and UVM, Design concepts and Analytical skills
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
Verilog code for basic circuits
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
Do not want to give it away but learn computer architecture well
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
There was no tehnical interview for no experience engineer
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