The asked about past work experience.
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
What is your experience with random constrained stimulus?
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
questions on digital electronics and verilog
completely based on system verilog and digital design concepts
Talk about resume, explain the detail. ask some related questions on the project.
Basics of UVM and SV
Grilled on my current work, System Verilog basics, UVM in depth, Comp Arch questions like Cache coherency.
Should be ready to write some logic (C/Verilog/System Verilog) on the spot
Energy - cost - time trade offs
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