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Verification Interview Questions
3,816 verification interview questions shared by candidates
What is Uvm methodology? Inline constraints
They mainly asked about relocation,teamwork and they check our softskills and ability to cable with their goals and effective work.
Initially the questions were based on my resume. Later some concepts of Verilog, like blocking-non blocking assignments. He asked me to write a small verilog code also.
Write dynamic array, MUX in Verilog
Write verilog code for asynchronous FIFO, verilog code for FSM.
All questions are based on the work experience and the job requirement
Questions on Design flow, Verilog , SV etc
Factory overiding methods in UVM
Do you familiar with UVM verification method？How's your script writing? (She asked nothing related to semiconductor or Integrated circuits).
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