SV constraint writing UVM TB writing
Verification Interview Questions
3,816 verification interview questions shared by candidates
1. Perform multiplication between two signed numbers? And many more
Digital Design - critical path, bit manipulation, logic questions, hardware design for your code using adders and gates Verification - assertions, constraints, coverage, OOPs (they will dig into this) virtual functions, polymorphism
How would you sort 10 integers in ascending order?
AI questions included about auto encoders, lstms, basics of neural network, convolutional neural networks etc.
1. Explain Channel length modulation 2. Explain body effect 3. Non idealities of MOS capacitance
All kinds of questions regarding Op-Amp My own research ADC/DAC, INL/DNL, distortion, etc. CMOS, Bipolar device basics (operation regions, I-V curve, equations, noise, etc)
How do you manage a situation with an unhappy client?
"know that what you are going to do here, you won't be able to reuse in other companies"
UVM environment and how it works?
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