uvm basic, ovm basic and python
Verification Interview Questions
3,816 verification interview questions shared by candidates
Most of the interview questions were from my resume and projects i have done. Some of the questions were based on VLSI design concepts
Difficult technical questions, very unforgiving when I got one question wrong, they ended the interview straight away after that.
power integrity understanding: including impedance threshold define and theory.
Write a Scoreboard for verifying the average of 5 previous values, where the data is coming sequentially, I.e 1 value at every posedge of clk.
polymorphism in system verilog and virtaul interfaces.
Design a bitstream pattern detection finite state machine in the HDL of your choice.
about how to build an adder
One medium question on leetcode. Absolute software engineer question.
It was strange interview I ever had. It was a telephonic interview and he asked me to explain system verilog code for small program, he was writing program as I was explaining him and he expect program to compile and run. Its all telephonic. which is strange. I did not like it and also not selected for next round
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