Digital and SV ,UVM verilog basis
Verification Interview Questions
3,816 verification interview questions shared by candidates
Describe Yourself, project related question.
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
My previous experience, basic assertions and fifo programming
How do I feel today
Which area are you specialized in?
Fota overview diagnostic flashing test and defect management procedure
Basic sv and uvm and some digital verilog.
They asked whether I am comfortable to do this verification work, and we just have to verify the data of the onboarding members in sale or customer department. Questions based on small data including basic excel.
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
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