A router transmits the data. If the data is destined for same address then the packets should arrive in the same order as it is transmitted. The packet sent second is not allowed to overtake the one sent first. But if the packets are destined for different address it can overtake the other packet. How will you verify this design. The packet does not contain any ID.
test bench architecture tesplan and verification
Everything on the resume and related stuff, C++, Pipling, GPU
How to verify your design ？about testbench design ...
What's C++ STL
What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.
First there was some basic questions on Computer Architecture, Verification Concepts and RESUME. After that she asked me to write code for hamming distance in prefered lang and UVM Code for driver component.
System verilog syntax
what is the most difficult person you met in your work? how did you handle that?
Questions were related to Digital design, RTL Verilog Coding, System Verilog and UVM
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