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Verification Interview Questions
3,816 verification interview questions shared by candidates
What challenges do you see in a cross-team effort for a verification project?
They gave me a design problem and kept on telling me to optimize it
UVM related questions.How to verify some components.How to verify a an old machine .X and Y dimensions of the screen in pixel was given.Was asked to write the test cases for the same.Was asked to a draw a fsm for a for traffic light signal .Questions related to clock skew,randomization and sorting algorithms
He asked me about Data hazards, Instruction sets , Examples of branch prediction , 32 bit adder design. WAR and RAW Instruction examples. Basic Computer architecture questions.
it was not that difficult.
Analog Circuits : Since I had some project work in PLLs I was asked where exactly a flipflop or a delay element should be added in the PLL loop, to resolve a glitch or to ensure that the PLL locks. Device Physics : How does mobility of electrons/holes vary with gate voltage in a MOSFET
Covered the resume.
All the questions were pretty basic and were related to fundamentals of logic design and verification.
Identify the circuit that the given FSM corresponds to, timing based questions, optimize the circuit. FSM was that of a simple counter
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