1) interrupt mask register (10 bits) - Each bit corresponds to 1 interrupt interrupt log register (10 bits ) - Each bit corresponds to 1 interrupt Interrupt mask register masks the interrupt from reaching the output pin i.e , the output pin shows 0 although theres an interrupt Interrupt log register logs the presence of interrupt , but the moment you do a read , the interrupt log reg bit goes to 0 . Best strategy to verify ?
What is deep copy and shallow copy in System Verilog? Can you tell about sequencer in UVM and what is the use of it? What is virtual interface and why it is used? Gave a Constraint and asked what will be the randomised values. Asked to write an assertion for a given scenario Asked to write a constraint such that it will generate even and odd numbers in sequence.
Code for fsm,digital electronics and sta
Draw an AND gate using transistors.
What are the limitations of current design methodologies?
Design a digital circuit that on every third cycle calculates the average between the first and the second posedge and write it in verilog
UVM and verification questions mainly
1) Tell me about yourself 2) Tell me about the projects on your resume
-General digital flow design -General UVM verification questions
1.difference between dynamic,static ,short circuit power diddipation ,where and how it happens ,how to reduce them 2. power reduction technoques at logic and architectute level 3. verilog
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