UVM TB questions, sequence, sequencer and driver protocol, SV randomization questions
Verification Specialist Interview Questions
3,822 verification specialist interview questions shared by candidates
pipeline processor architecture, hazard, shared memory problem, cache issues—remote repeated words both in SystemVerilog. I answered how to do it in python, but he insisted Con using c or SystemVerilog. In the last question, he asked me why I choose design verification. The whole procedure lasts about 53 minutes, quite tense I would say. I did not answer the memory coherence and delete repeat words in C. I would say I did not do it well. Hoping this could help others to get job. Just preparing questions.
Memory allocation
2.fsm design for counters
5.structre of a processor, pipelining, and cache coherence based questions
What is an asynchronous FIFO and why do we need (n+1) bit pointers.
Pipeline, risc-v, stalls, forwarding unit, hazard detection unit.
That's all i can share . Practice your basics. All the best !
Decode a CMOS transistor diagram (complex)
Some basic questions/tasks about C programming (pointers, arrays..), design task for receiving data bytes from the transmitter (C programming), Asked to explain different parts of some old SOC configuration. For people studying only Electronics I would suggest going through Software Engineering lectures from other courses to know about how memory is managed in a SOC and CPU. Ideally read about the Architecture of CPU and Microcontrollers as I was asked this in all 3 Interviews with ARM. I only studied Electronics and had no courses related to this except when we briefly looked into simple microcontrollers without going into detail so it was good decision going through Software Engineering course notes before the interview.
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