Scripting and programming interview was about file parsing and automation (Analyse the code, find the error, correct it) General keep an eye on digital design concepts like FSMs, Clock and Timing, CDC, etc.
Verification Specialist Interview Questions
3,820 verification specialist interview questions shared by candidates
If two cells are reporting a DRC violation, how could/would you solve it
Constraints and system verilog assertions
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
- code coverage: types, why, how to collect, analysis. Functional coverage: why, how, analysis.
- structure of a typical verification environment, explain each block. Verification closure process. Top/chip level verification, block level reuse techniques.
- problem solving: 1) write systemverilog properties to verify a given, simple protocol. 2) compute the optimal FIFO depth given the in and out timing specs. 3) Write the RTL for a FSM then synthesize it.
Mostly about verilog, Problem solving skills
Verilog based basic questions , SV and UVM questions
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