What is a state machine?
Verification Specialist Interview Questions
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A router transmits the data. If the data is destined for same address then the packets should arrive in the same order as it is transmitted. The packet sent second is not allowed to overtake the one sent first. But if the packets are destined for different address it can overtake the other packet. How will you verify this design. The packet does not contain any ID.
How to verify your design ？about testbench design ...
What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.
what is the most difficult person you met in your work? how did you handle that?
Everything on the resume and related stuff, C++, Pipling, GPU
What are the types of assertions in System Verilog? What is a linked list?
Mesi Moore and mealy Coding
Given a function in C++, describe the intended purpose, what it returns, and fix the code so it actually returns what it is meant to return.
test bench architecture tesplan and verification
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