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Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Told to design a layout through a very slow laptop, be prepared. asked about parasitics in layout design, and effect of high voltage on MOS and what should you do.
Previous challenges as a physical design engineer, lot of questions about the .libs and encounter commands.
Scripting skills in Perl : regular expressions Logical Effort, Projects done in Master's
Given a diagram, how would you verify a design/check output data. Computer arch basics and design questions
functional, code coverage ,priority encoder explanation, SV
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
Detect that N numbers have arrived based on a control signal. Flag the average of all the N numbers once the N-numbers have arrived.
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
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