Setup-Hold timing inter-relationship question, framed by way of max frequency of operation
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Provided a waveform and asked to design a circuit for that.
1. Some simple random stimulus with specified constraints
Cache
Retiming for a 5 input OR
FIFO Design
Sequence detecting FSM, coding it in Verilog
Design Questions and some logic questions
Logical design, physical design, perl, System verilog (UVM)
Questions in digital design, timing violations, metastability
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