how would you code an adder in verilog
Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
Q: SystemVerilog syntax questions Q: Design a clock in verilog without any existing clock signals Q: Some flip-flop/latch design questions at clock-domain crossing.
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SV and UVM related questions and ur understanding
Questions on Digital electronics, CMOS, Physical Design and LVS
About system verilog , verilog, digital electronics
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Code C++ - to print Fibonacci series using C++
1. They asked me to explain a flip flop function with wave forms and an rtl programme in Verilog. 2. I was given a sequence of input waveform and was asked to design a state diagram and also to write an rtl code in Verilog 3. Functionalities of the Universal gates, clocking domains, STA, few analogue questions 4. To explain the previously done projects of my academic qualification in detail
For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?
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