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Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
Write verilog code for any flipflop. variations were also asked.
What is your experience with random constrained stimulus?
When in your previous work did you wish you behaved differently?
Pipeline , caches, TLB , virtual memory
Why is program block needed. What is clocking block. Program for clock without always. Differnce between always_combo and always.
If you have a DC power supply in series with a 1k resistor and a 6k resistor, give the equation that described the voltage across the 6k resistor. Switch the 6k resistor for an inductor, what is the voltage across the inductor? Switch the inductor for a capacitor, what is the voltage across the 1k resistor? Change de the 1k resistor for a cap identical to the other one, what is the voltage drop across each cap? Change one of the caps to make it double the capacity of the other one, what is the voltage drop across each cap?
What did you do in your last job?
show how code coverage and function coverage works. explain with code
APB and AXI protocol explation with all signals.
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